Some types of semiconductor memory devices are SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), flash memory, and ferromagnetic RAM. These memory devices can have significantly different operational properties, such as those shown below in Table 1, and accordingly may be appropriate for use in some electronic devices, but not others.
TABLE 1SRAMDRAMFLASHFeRAMMRAMReadHigh speedHalf speedHigh speedHalf speedHalf ~ High speedWriteHigh speedHalf speedLow speedHalf speedHalf ~ High speedNon-volatilityNot existNot existExistHalfExistRefreshNot NeedNeedNot NeedNot NeedNot NeedSize of Unit CellLargerSmallerSmallerHalfSmallerLow Voltage for OperationPOSSIBLELIMITEDIMPOSSIBLELIMITEDPOSSIBLE
FIG. 1A is a circuit diagram of a unit memory cell of a prior art full CMOS SRAM, in which a P-channel MOSFET is used as a pull-up device. Such SRAM devices may provide high speed read and write operations and/or low power consumption. However, as shown in FIG. 1A, the unit cell has six transistors, which may limit the integration density of such unit cells.
FIG. 1B is a circuit diagram of a cell array of a prior art DRAM. The unit cell of the DRAM has one transistor and one capacitor, the DRAM may have a unit cell area of about 10F2, which can be much smaller than the unit cell area of the SRAM (“F” indicates a minimum feature size). Accordingly, the DRAM may have a higher unit cell integration density than the SRAM. In contrast to SRAMs, DRAMs may need a refresh operation every several milliseconds to prevent loss of information due to, for example, leakage of stored charge.
Some electronic devices need non-volatility memory in which stored information is maintained after power for the memory is removed. Flash memories and ferroelectric memories may be used to provide non-volatility memory in such electronic devices.
FIG. 1C is a circuit diagram of a cell array of a prior art NAND flash memory. Because the illustrated NAND flash memory does not include a cell capacitor and a contact in every unit cell, it may have a unit cell area of 4˜8F2, which may be smaller than the unit cell area of a DRAM. Accordingly, NAND flash memory may have a higher integration density than DRAM devices. However, NAND flash memory may need a high driving voltage, such as, for example from 5 to 12 volts in a write mode, and may have a low erase speed. Also, integration density of the NAND flash memory may be reduced by the use of a pumping circuit to elevate the driving voltage. Flash memory may also provide a limited number of rewritable operations, such as, for example 105 to 106 rewrites.
A ferroelectric memory may use, for example, one transistor and one capacitor per unit cell, similar to DRAMs. A ferroelectric memory can be made non-volatile by using a ferroelectric material in the capacitor. Read operations may have a destructive affect on information in memory cells, so that a rewrite operation may be needed after a read operations. Ferroelectric memories may also provide a limited number of write operations, and may provide relatively average memory access speeds. Ferroelectric memories can be difficult to manufacture because of, for example, reactivity of the ferroelectric materials with hydrogen, high temperatures that may be used for annealing processes, and scalability and cell voltage issues.
Magnetic RAM or Magnetoresistive RAM (MRAM) can be used to provide non-volatile memory that may not be write cycle limited, may allow high integration density, may provide fast memory access operations, and may use a lower voltage relative to ferroelectric memories.
A prior art MRAM is hereafter described with reference to FIGS. 2 to 4. FIG. 2 is a plan view of a part of a cell array of a prior art MRAM. FIG. 3 is a sectional view taken along line I–I′ of FIG. 2. FIG. 4 is a perspective view of a structure of a prior art MRAM with a Magnetic Tunnel Junction (MTJ).
Referring to FIGS. 2 to 4, a device isolation region 12 defines an active region 11 in a semiconductor substrate 10. A plurality of gate electrodes or word lines 15 intersect over the active regions 11 and the device isolation region 12. Each of the active regions 11 perpendicularly intersects over a pair of gate electrodes 15, so that if the active regions 11 are arranged in a row direction (X-axis direction), the gate electrodes 15 are arranged in a column direction (Y-axis direction). A common source region 16s is formed in the active region 11 between the gate electrodes 15, and the drain regions 16d are formed in the active regions 11 on both sides of the common source region 16s. A cell transistor of the MRAM is thereby arranged at an intersection point of the active region 11 and the gate electrode 15.
A whole surface of the resultant substrate including the cell transistor is covered with an interlayer insulating film 20. A plurality of digit lines 30 are parallel to the gate electrodes 15 in the interlayer insulating film 20. A plurality of bit lines 50 are formed parallel to the active region 11 to intersect over the gate electrode 15, on the interlayer insulating film 20 and over the digit lines 30. A magnetic tunnel junction (MTJ) 40 is formed between the bit line 50 and the digit line 30. A lower electrode 35 is between the MTJ 40 and the digit line 30 and extends to an upper portion of the drain region 16d. The MTJ 40 contacts a lower surface of the bit line 50 and an upper surface of the lower electrode 35. A vertical wiring 25 is formed in the interlayer insulating film 20 and electrically connects the drain region 16d to the lower electrode 35. The vertical wiring 25 can also include a plurality of plugs having a sequentially stacked structure. A source line 28 is connected to an upper surface of the common source region 16s via a source plug 26 that is connected therebetween.
The MTJ 40 may have a sequentially stacked structure of a pinning layer 42, a fixed layer 44, an insulating layer 46 and a free layer 48. The resistance of the MTJ 40 can substantially vary based on the relative magnetization directions of the fixed layer 44 and the free layer 48 (e.g., same or opposite magnetization directions). Consequently, resistivity of the MTJ 40 can be used to indicate information in a MRAM. Generally, the magnetization direction of the fixed layer 44 is not varied during a reading/writing operation. A multi-layered or single layered pinning layer 42 can fix the magnetization direction of the fixed layer 44. The magnetization direction of the free layer 48 can vary relative to the magnetization direction of the fixed layer 44. For example, the magnetization direction of the free layer 48 can be the same or reversed to that of the fixed layer 44.
Information may be read from a cell by selecting the corresponding word line 15 and bit line 50, and then measuring current flowing therethrough. Current magnitude may substantially vary depending on the relative magnetization directions of the fixed layer 44 and the free layer 48. The relative current magnitude can represent stored information (e.g., binary values). Information can be written to a cell by varying the magnetization direction of the free layer 48, such as by creating a magnetic field from the current flowing through the bit line 50 and the digit line 30.